On 3rd December 2020, Plinio Bau defended his thesis by zoom. His work was realized at Laplace laboratories and IRT Saint Exupéry, under the supervision of GEET doctoral school.
The high quality and the relevance of Plinio’s thesis contributed to get significant results as a part of the EpowerDrive project.
Thesis Subject
“CMOS Active Gate Driver for Closed-Loop dv/dt Control of Wide Bandgap Power Transistors ”
About this thesis
Wide bandgap (WBG) power transistors such as SiC MOSFETs and GaN HEMTs are a real breakthrough in power electronics. These power semiconductor devices have lower conduction and switching losses than their Silicon competitors. However, the fast switching transients can be an issue in terms of Electromagnetic Interferences (EMI). Consequently, one must slow down the switching speeds of WBG transistors to comply with EMI limitations, which reduces their advantages in terms of higher switching frequencies and lower total losses. In this work, an active gate driver is proposed to control the switching speed of wide bandgap semiconductor power transistors. An innovative closed-loop control circuit makes it possible to adjust separately the dv/dt and di/dt during the switching sequences. Overall, the dv/dt values can be reduced to comply with system-level limits of EMI, with less switching losses than existing methods. The proposed method is thoroughly investigated, with analytic and numerical models to assess the key performances: feedback loop bandwidth, optimal circuit design, area consumption. Selected and optimal designs are implemented in two integrated circuits in CMOS technology which demonstrate delay times below the nanosecond. With such performances, it has been shown experimentally that it is possible to actively control switching speeds higher than 100 V/ns under voltages of 400 V.
EpowerDrive Project
The objective of this project is to offer to members, technological and methodological solutions to reduce the volume, increase the power density and the reliability of electromechanical chain. The perspectives proposed are the development of multi-physical sizing tools, filters input/output optimized, power cores based on high gap components, and associated components (drivers), control of loss in high-speed electric machine and to studying architectures fault-tolerant. Technological demonstrators about test equipment updated will validate all these works, in order to increase the power and to offer a “reference” testing platform at the service of this projects and members.
Moreover, this project include also the possibilities of discover the potential of additive manufacturing.
JURY
| Bruno ALLARD | Rapporter | Professor / Ecole Centrale de Lyon Laboratoire Ampère |
| Nadir IDIR | Rapporter | Professor / Université de Lille L2EP |
| Francois COSTA | Examiner | Professor / Université Paris Est Créteil laboratoire SATIE |
| Radoslava MITOVA | Examiner | Research Engineer / Schneider Electric |
| Frédéric RICHARDEAU | Examiner | Researcher / Institut National Polytechnique de Toulouse LAPLACE |
| Nicolas ROUGER | Thesis Director | Professor/ Institut National Polytechnique de Toulouse LAPLACE |
| Marc COUSINEAU | Thesis co-Director | Lecturer / Institut National Polytechnique de Toulouse LAPLACE |
| Bernardo COUGO | Industrial co-Director | Senior Expert / IRT Saint Exupéry |
| Olivier CREPEL | Invited | Engineer / Airbus Central R&T |
PUBLICATIONS
Plinio Bau, Marc Cousineau, Bernardo Cougo, Frédéric Richardeau, Nicolas Rouger. Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN – 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Sep 2020, Vienna ( virtual ), Austria. pp.106-109
Plinio Bau, Marc Cousineau, Bernardo Cougo, Frédéric Richardeau, Nicolas Rouger. CMOS Active Gate Driver for Closed-Loop d v /d t Control of GaN Transistors
IEEE Transactions on Power Electronics, Institute of Electrical and Electronics Engineers, 2020, 35 (12), pp.13322-13332.
Bau Plinio, Marc Cousineau, Bernardo Cogo, Frédéric Richardeau, Vinnac Sébastien et al. Sub-nanosecond delay CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors
31st IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2019, Shanghai, China.
Plinio Bau, Marc Cousineau, Bernardo Cougo, Frédéric Richardeau, Nicolas Rouger. Contrôle ultra-rapide et intégré de dv/dt en boucle fermée lors de l’amorçage de transistors à semiconducteurs grand-gap
SGE 2020, Symposium de Génie Electrique, Nov 2020, Nantes, France